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 Need Recomendation for Motherboard & CPU's for dual PII or PIII
: Greg Leblanc <glebl...@my-deja.com> wrote:

: : In certain situations.  The Ultra-sparc is the most distinguished CPU in
: : high CPU count.  The Alpha maxes out at 14 (because of the bus
: : arcitecture,  I think) and I don't know anything about the PA-RISC,
: : except that HP-UX is a {*filter*} to work with.   The UltraSPARC is a bit
: : behind the others in clock speed, but if you put 64 of them together,
: : who cares?

: tell SGI, then, with their MIPS o2000 systems.  I believe that 256 and
: 512 cpu systems (!!) are quite possible.  nothing sun has can even
: come close.  by a long shot.

: and Cray went with clusters of alpha chips.  I'm quite sure they
: exceeded 14 alphas in their final systems ;-)

Yep, right now I'm using a cray(owned by SGI) T3E using 512 of them.

Sean



 Sun, 24 Mar 2002 03:00:00 GMT   
 Need Recomendation for Motherboard & CPU's for dual PII or PIII

These are all parallel machines, not SMP.

The SGI origin 2000 is a CC-NUMA architecture, and scales to 64 CPU's with
hypercube topology, or you can get 4 of the 32-CPU nodes crossbar'ed together to
make a 128 - this version has a Cray badge. Perhaps they now do larger models.
It does have certain single system image aspects, as does the IBM SP/2, but
memory access is highly non-uniform.

The Cray T3x is a pure parallel machine (3d toroidal toplology), with no SSI
features. There are only *two* CPU's per node, each running its own microkernel
(Unicos/MX). Hardly SMP! In Linux terms, this is like a Beowulf cluster, not a
single computer.

Using vector supercomputer style memory systems, 32 to 64 CPU's per node *with
true SMP* seems to be about the limit - HP, Cray, NEC and Sun offer such
systems.

Dave

--
David Crooke, Austin TX, USA. +1 (512) 795 0805
Bibendo ergo sum.



 Sun, 24 Mar 2002 03:00:00 GMT   
 Need Recomendation for Motherboard & CPU's for dual PII or PIII
In article <37FB8D7F.9074F...@dcc.vu>,

Do I have the CPUs/OSs in these right?  HP would be their PA-RISC and
HP-UX.  Cray would be Alpha? and IRIX?  NEC, I don't know about.  Sun is
the E10K, running Solaris.

What about the MONSTER x86 boxes that sequent makes(made? are they IBM
Now)?  I know that at least some of them have an SMP arcitecture, and
really low overhead.  Are their really large systems parallel, or SMP?
     Greg

--
It's pronounced "{*filter*}" not "scuzzy"!

Sent via Deja.com http://www.**-**.com/
Before you buy.



 Tue, 26 Mar 2002 03:00:00 GMT   
 Need Recomendation for Motherboard & CPU's for dual PII or PIII
In article <7tjuq9$uj...@nnrp1.deja.com>,
Greg Leblanc  <glebl...@my-deja.com> wrote:

They're Intel, but not x86. IBM now owns Sequent. They use NUMA technology.

What is SMP?

Adam
--
Adam J. Finkelstein
ad...@radix.net
http://metalab.unc.edu/bees/adamf



 Tue, 26 Mar 2002 03:00:00 GMT   
 Need Recomendation for Motherboard & CPU's for dual PII or PIII

Sorry, I have to call bullshit on that one I'm afraid - most CISC cpu's do use
microcode, most RISC cpu's do not - almost by definition. One of the design
concepts of RISC was to cut out the middle man in this respect, and effectively
have the compiler generate the microcode. This was one of the ways they achieved
an instruction per clock tick. The original ARM is 32-bit and only has 27,300
transistors - where do you hide microcode in there? :-)

The Intel Pentium (MMX, II, III) internally turns a stream of x86 instructions
into a (longer) stream of microcode, which is what the processor core actually
executes. Admittedly, this is nearly a 1:1 ratio with common instructions, but
the wrong x86 sequences can slow it down *a lot*. As I said, what a mess.

The definition of what is and isn't microcode is arguable - the old 60's and
70's machines often ran whole subroutines of microcode for each macro
instruction (IBM 370, PDP-11, VAX) and some even had a layer under this called
"nanocode". The Pentium's way of doing things is clearly far more efficient than
that, but there is nevertheless an unnecessary translation overhead. If you're
going to build a hardware JIT compiler, why not make it a Java VM one? :-)

Intel and AMD have worked wonders with this dinosaur, but the hangovers in the
x86 instruction set (16 bit registers, segment and offset, non-uniform register
sets) still mitigate against reasonably calling *any* implementation of it
"RISC", irrespective of performance.

Dave
--
David Crooke, Austin TX, USA. +1 (512) 795 0805
Bibendo ergo sum.



 Wed, 27 Mar 2002 03:00:00 GMT   
 Need Recomendation for Motherboard & CPU's for dual PII or PIII

Actually, some (most?) Sequent Symmetry machines are x86 based - Edinburgh
University still has one as their main generic Unix service, with a mixture of
486 and Pentium nodes.

SMP is the conventional multi-processor design, an alternative to things like
NUMA - SMP stands for "Symmetric Multi-Processor" and basically means that you
have a number of CPU's sharing a common RAM, where each CPU has equally fast
access to all of the RAM.

The problem with SMP is that it is inherently unscaleable - the bandwidth of the
RAM has to be shared between the CPU's, when it is already less than ideal for
one CPU. An added problem in this day and age of heavy reliance on cache is
*cache coherency* - making sure that if one CPU doesn't read data from RAM that
is out of date because another one has already changed the copy in its cache. To
work without hampering the cache performance, this requires interconnection of
those caches and (relatively) complex strategies like the Berkley protocol,
which must necessarily be implemented in hardware

Eight CPU's is generally regarded as the limit for SMP on non-vector systems;
even that can be problematic, as the rather tired performance of Intel's 440NX
8-way SMP systems shows (the inter-cache bus is only 100MHz IIRC).

Ironically, since they already have technology in place for complex scheduling
of memory accesses and for splitting the memory into many banks to increase the
bandwidth, vector machines actually scale *better* for SMP than normal systems,
and several successful 32-way SMP vector designs exist (NEC, Fujitsu, Cray)

NUMA stands for "Non-Uniform Memory Access" - the memory is split into pools,
each of which is directly connected to a small number of CPU's; access to memory
in other pools is through a slower interconnect bus, rather like in an MPP
(conventional parallel) system. The difference with NUMA systems is that the
management of remote vs local memory is handled by the hardware and the
operating system, and like virtual memory, programmers need not worry about it
except for performance tuning.

The archetypal modern cc-NUMA (cache coherent NUMA) system is the SGI Origin.

--
David Crooke, Austin TX, USA. +1 (512) 795 0805
Bibendo ergo sum.



 Wed, 27 Mar 2002 03:00:00 GMT   
 
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